Optimizing load-transient response in PoL with PID and NLR control loops

Load steps cause under- and overshoot

All control loops, analog or digital, have a response time to changes so that with a load current step upward, for example, the PoL output will drop until the control loop “catches up” and restores the output to the correct value. The amplitude and duration of the drop (or rise in the case of load decreasing) must be carefully controlled so that the load IC voltage limits are not exceeded. With processors, for example, current steps can be tens of amps from idle to active states with very fast rise and fall times, exacerbating the problem. The change in PoL output voltage with load steps is caused by resistive elements in the power train such as tracks and wires and also by the PoL output inductor, which resists current change by generating voltage according to the familiar E=-L*di/dt. Inductance in the tracking from the PoL to the load IC adds to the effect as well. Capacitors on the output of the PoL are necessary to provide energy storage during the switching cycle off-period and help to reduce the voltage transients with load steps.

However, a resonant circuit is formed by the combination of series inductance and parallel capacitance, with a gain that peaks at the resonant frequency with a rapid phase change to -180° delay. With the inherent 180° phase shift of a negative feedback system, the control loop delay can total 360° at some frequency, producing positive feedback and instability.

“Compensation” of the feedback signal is therefore necessary by tailoring the error amplifier frequency response to keep bandwidth high for best load-transient response while maintaining loop stability. This is characterized by a “gain margin,” typically at least -6 dB, when the power train phase delay does reach -180° and a “phase margin,” typically at least 60° less than the full 360° at the frequency where gain drops to unity. Ideally, the gain should be reducing by -20 dB/decade at the unity gain point.

Bode plot showing magnitude and phase versus frequency, with the magnitude curve decreasing at –20 dB per decade, a phase margin greater than 70 degrees at the crossover point, and a gain margin of 20 dB indicated near the high‑frequency region.

Figure 1: Typical target control loop response

In analog compensation schemes, parallel and series resistor-capacitor networks are employed around the error amplifier to shape the feedback frequency response. These networks have “corner frequencies,” which represent “poles” or “zeroes” in the loop transfer function, which can be graphically added in a “bode plot” to give a visual indication of loop bandwidth and gain/phase margin achieved. In digital control schemes, the feedback voltage and error signal are manipulated using the logic and arithmetic functions of a processor to achieve the same effect, so it is useful to talk in terms of the mathematical representation of the desired compensation frequency response. In this case, traditional control theory can be used with a proportional-integral-differential (PID) scheme; three separate error correction signals are generated, one proportional to the instantaneous difference between the reference and the desired output, one representing the time integral of the difference or summation of difference over past time, and one representing the differential or rate of change of the error signal as an indication of its trajectory in the future. Different weightings K_p, K_i and K_d of the three PID terms can then be added, to approach an optimum loop response. The overall control function u(t) for error voltage e is then:

$Mathematical expression showing the PID control law, where the output $$u(t)$$ is the sum of a proportional term $$K_p e(t)$$, an integral term $$K_i \int_0^{t} e(t')\, dt'$$, and a derivative term $$K_d \frac{de(t)}{dt}$$.$

Digital control also allows other response compensation schemes, even non-linear, and weightings can be altered dynamically in response to changing load conditions.

The digital POLs usually have a standard configuration with a robust control loop compensation setting (PID setting) which allows for a wide range operation of input and output voltages and capacitive loads. For an application with a specific input voltage, output voltage, and capacitive load, the control loop can be optimized for a robust and stable operation and with an improved load transient response.

Learn more in Flex Power Modules application note 306: Optimizing load transient response for PID and NLR control

This optimization will minimize the amount of required output decoupling capacitors for a given load transient requirement yielding an optimized cost and minimized board space. Fortunately, some suppliers provide software for this purpose. An example is the Flex Power Designer software, available free of charge from Flex Power Modules.

Learn more in Technical paper 022: Loop compensation and decoupling design with “The Loop Compensator”

Optimizing PoL control loops with Flex Power Designer software

The starting point for loop compensation is the load requirement. A typical example is shown in Table 1 for an IC with a 1 V rail.

Table 1: Typical processor IC power rail requirements

Load transient requirement	Value used in example
Max deviation	30 mV (3% of 1 V Output)
Recovery time	100 µs
Recovery limit	10 mV (1% of 1 V Output)

The actual load steps and the slew rate encountered depend on the application, so assumptions have to be made initially until real-life tests are conducted. In our example, the values of Table 2 are assumed.

Table 2: Transient load assumed characteristics

Transient response simulation parameters	Value used in example
Load Current transition	10 A – 20 A
Slew rate	5 A/µs
Step period	2 ms
Vout droop	0 mV/A

Once a PoL type is selected from the Flex range, BMR464 in this example, the components of an output filter between the PoL and load are specified. These include recommended output capacitors for energy storage, capacitors for noise filtering and any intentional or parasitic series inductance. A typical network is shown in Figure 2.

Schematic diagram of a point‑of‑load (POL) regulator followed by an output network featuring an inductor, multiple decoupling capacitors (MC1, MC2, LC1, LC2) with associated ESR values, interconnect parasitics including RWIRE and L1, and the load connected at the far right with +S and –S sense lines.

Figure 2: Typical PoL output filter network

The software can apply different degrees of feedback compensation for the load network and target transient response with “robust” and “optimized” levels available. The default simulation can be plotted on a graph and typically shows a heavily damped and stable but slow response with voltage deviation above the target values, shown as dotted lines in Figure 3a. “Robust” simulation chooses preset PID weightings to improve response time to the target values but still does not achieve the voltage deviation requirements (Figure 3b). Selecting “optimized” simulation with an iterative calculation of PID weightings improves the voltage deviation and response time still further (Figure 3c). While this gives a good margin against the target voltage deviation and response time, the performance will be very sensitive to component tolerances and errors in assumed parasitic values, and could be unstable under some conditions.

Figure 3a: Robust load-transient response

Line graph labeled “Figure 3a” showing voltage versus time, with a solid response curve and a dashed requirement curve. The plot illustrates a deep initial voltage dip followed by a gradual rise, then a sharp voltage overshoot at around 1 ms, returning slowly toward steady state. Shaded horizontal bands highlight different voltage ranges.

Figure 3b: Default load-transient response

Line graph labeled “Figure 3b” showing voltage versus time, with a solid blue response curve and a dashed requirement curve. The plot illustrates a transient voltage dip followed by a peak and gradual return to steady state, with shaded horizontal bands highlighting different voltage ranges.

Figure 3c: Default load-transient response

Voltage transient response plot showing measured output behavior versus requirement limits during load step events, illustrating overshoot, undershoot, and stabilization over a 2 ms interval.

Non-linear compensation response improves voltage deviation with load steps

To get closer to the target specification for voltage deviation, many of Flex Power Modules’ PoLs such as the BMR462/463/464/466 include a non-linear response (NLR) function. In this scheme, alongside normal PID control, the feedback voltage is monitored on a cycle-by-cycle basis and if it falls outside preset limits, the power train is set to immediately source or sink current with extra or blanked pulses respectively. This helps to correct the output deviation, effectively increasing the feedback loop bandwidth.

With optimized PID and NLR control, a real-time plot of voltage deviation with the conditions defined gives Figure 4, showing recovery time well within the target 100 µs with a peak deviation just a little more than our +/-30 mV target at 65 mV peak-to-peak.

Oscilloscope screenshot showing two waveforms, with the upper green trace displaying a transient spike and ripple, and on‑screen measurements indicating approximately 65 mV peak‑to‑peak, 25% overshoot, a maximum of 34 mV, and a minimum of −31 mV; the lower yellow trace shows corresponding step changes in the signal.

Figure 4: Measured response of the example PoL and load system

Diagram comparing perfect versus real static load regulation during load current steps, highlighting voltage deviation, transient response, and reduced peak-to-peak variation in practical power regulation systems.

Figure 5: Allowing finite static load regulation improves dynamic voltage deviation

In Figure 4, the output voltage is settling to within a few millivolts of the nominal value after each load-step edge.

The Flex Power Designer software allows this static regulation to be adjusted so that there is some “droop” with increasing load. This can actually improve overall dynamic regulation, as shown in Figure 5, to potentially meet the target voltage deviation specification.

Summary

Digital control of PoL regulators opens up a world of possibilities to optimize static and dynamic load-transient response to suit today’s demanding applications. Software such as Flex Power Designer with its user-friendly GUI makes the optimization process quick and easy.